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Inter-integrated circuit (I 2 C) interface
RM0008
Bit 2 TRA : Transmitter/receiver
0: Data bytes received
1: Data bytes transmitted
This bit is set depending on the R/W bit of the address byte, at the end of total address
phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start
condition, loss of bus arbitration (ARLO=1), or when PE=0.
Bit 1 BUSY : Bus busy
0: No communication on the bus
1: Communication ongoing on the bus
–Set by hardware on detection of SDA or SCL low
–cleared by hardware on detection of a Stop condition.
It indicates a communication in progress on the bus. This information is still updated when
the interface is disabled (PE=0).
Bit 0 MSL : Master/slave
0: Slave Mode
1: Master Mode
–Set by hardware as soon as the interface is in Master mode (SB=1).
–Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
(ARLO=1), or by hardware when PE=0.
24.6.8
Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note:
1
2
F PCLK1 is the multiple of 10 MHz required to generate the Fast clock at 400 kHz.
The CCR register must be configured only when the I2C is disabled (PE = 0).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
F/S
DUTY
Reserved
CCR[11:0]
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Bit 15 F/S: I2C master mode selection
0: Standard Mode I2C
1: Fast Mode I2C
Bit 14 DUTY: Fast mode duty cycle
0: Fast Mode t low /t high = 2
1: Fast Mode t low /t high = 16/9 (see CCR)
Bits 13:12 Reserved, forced by hardware to 0.
650/995
Doc ID 13902 Rev 9
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